This invention relates to clock data recovery circuitry and phase locked loop circuitry. More particularly, this invention relates to providing clock data recovery circuitry and phase locked loop circuitry with dynamically adjustable bandwidths.
An increasingly important type of signaling between devices is signaling in which the clock signal information is embedded in a serial data stream so that no separate clock signal needs to be transmitted. For example, data may be transmitted serially in “packets” of several successive serial data words preceded by a serial “header” that includes several training bits having a predetermined pattern of binary ones and zeros. The clock signal information is embedded in the data signal by the high-to-low and/or low-to-high transitions in that signal, which must have at least one high-to-low or low-to-high transition within a certain number of clock signal cycles. At the receiver the clock signal is “recovered” from the data signal. The clock signal is then used to recover the data from the data signal. For convenience herein this general type of signaling will be referred to generically as “clock data recovery” or “CDR” signaling.
CDR signaling is now being used in many different signaling protocols. These protocols vary with respect to such parameters as clock signal frequency, header configuration, packet size, data word length, number of parallel channels, etc. Such signaling protocols include (1) industry-standard forms such as XAUI, InfiniBand (IB), Fibre Channel (FC), Gigabit Ethernet, Packet Over SONET or POS-5, Serial RapidIO, etc., and (2) any of a wide range of non-industry-standard or “custom” forms that particular users devise for their own uses. Such custom protocols often have at least some features similar to industry-standard protocols, but deviate from industry standards in other respects.
A programmable logic device (“PLD”) is a general-purpose integrated circuit device that is programmable to perform any of a wide range of logic tasks. Rather than having to design and build separate logic circuits for performing different logic tasks, general-purpose PLDs can be programmed in various different ways to perform those various logic tasks. Many manufacturers of electronic circuitry and systems find PLDs to be an advantageous way to provide various components of what they need to produce.
CDR signaling is an area in which it would be highly desirable to have the ability to use PLDs to avoid having to always design and build CDR transmitters and receivers that are specific to each of the many different CDR protocols.
In addition to CDR signaling, phase-locked loop (PLL) circuitry is another area in which it would be highly desirable to have the ability to use PLDs to avoid having to always design and build PLL circuits that are specific to each of the many different protocols. PLL circuitry can be part of CDR circuitry or can be separate from CDR circuitry (e.g., on PLDs that do not have CDR circuitry).
In conventional CDR circuitry and PLL circuitry, each circuit is programmed to have a fixed loop bandwidth that is based on the specific requirements for a given system or protocol. The bandwidth indicates the performance of the CDR circuitry or PLL circuitry. More particularly, the bandwidth indicates how quickly and efficiently the CDR circuitry or PLL circuitry performs in, for example, receiving and processing data, adjusting to changes in the input frequency, recovering data at the output, and filtering out noise from different sources.
Different systems or protocols have different bandwidths requirements. Programmability of a PLD provides for one CDR circuit or PLL circuit that can support different systems or protocols with different bandwidth requirements. Each system or protocol that uses CDR circuitry or PLL circuitry has specific requirements for a variety of parameters. For example, in a synchronous communications system, the CDR circuitry or PLL circuit must meet specific requirements for jitter tolerance, jitter transfer, and jitter generation. Jitter tolerance refers to a maximum amount by which the input data signal is allowed to deviate from its ideal position due to noise while still generating a correct output data signal. To meet jitter tolerance requirements at the receiver, different systems or protocols impose different minimum bandwidth requirements for the CDR circuitry or PLL circuitry. Jitter transfer refers to the ratio of the output noise to the input noise. To meet jitter transfer requirements, different systems or protocols impose different bandwidth requirements for the CDR circuitry or PLL circuitry in order to achieve as small a noise ratio as possible. The smaller the noise ratio, the better the performance of the CDR circuitry or PLL circuitry. Jitter generation refers to the amount of noise generated at the output of the transmitter and receiver. To meet jitter generation requirements, different systems or protocols impose different maximum bandwidth requirements for the CDR circuitry or PLL circuitry. Programmability of the bandwidth allows the different parameters to be changed to meet the specific requirements for a given system or protocol. Programmability of the bandwidth also allows the bandwidth to be changed based upon changes in the input frequency or data rate within a given system or protocol. Programmability of the bandwidth further allows the bandwidth to be changed based upon the dominant source of noise. Upon determining whether noise from the input or the power supply is more dominant, the bandwidth can be programmed accordingly in order to filter the more dominant noise.
The bandwidth of the CDR circuitry or PLL circuitry can be programmed by the PLD using configuration random access memory (CRAM) control bits. In response to processing data in a new system or protocol, the PLD often needs to be reconfigured in order to reprogram the CDR circuitry or PLL circuitry with a new bandwidth. In view of the foregoing, it would further be desirable to provide CDR circuitry or PLL circuitry with a dynamically adjustable bandwidth.